Interconnections between different parts of an integrated circuit increasingly affect the performance, reliability and power consumption of the integrated circuit. The geometry and characteristics of these interconnections are an important characterization of the operation of the resulting semiconductor. One structure which interconnects the different levels of interconnections is called a via. Vias have been traditionally made of aluminum wiring materials.
There is a demand in the art for smaller sized vias. This demand has led the present inventors to consider copper for use in forming the vias. Copper has a lower resistivity and higher reliability than previously-used materials such as aluminum.
These materials have been traditionally deposited by a deposition technique. One difficulty with copper has been the low vapor pressure of copper halides. This makes it difficult to pattern these materials.
Copper has been patterned using reactive ion etching ("RIE"), or damascene. Damascene etches grooves and vias into the dielectric and then deposits copper into the grooves. Chemical vapor deposition ("CVD"), however, has been used to provide a good filling for both the grooves and vias. CVD forms a vapor deposit on a reactive precursor. CVD of copper requires special equipment and expensive precursors. This has limited the interest in copper CVD.
The present invention describes a technique which allows copper to be deposited to form vias and interconnects within desired areas without requiring the difficult CVD process. A physical vapor deposition (PVD), preferably sputtering, is used along with important materials selections and techniques to allow selective deposition of the materials.
The present technique teaches selectively depositing copper metallization to fill vias and other high aspect ratio features. The technique according to the present invention uses selective sputtering and resputtering during the physical vapor deposition. The sputtered areas collect copper and hence build up a layer of copper in those areas. The resputtered areas have a steady state copper overcovering, which forms a thinner layer, e.g., a monolayer, over those resputtered areas. Importantly, this thinner layer increases in thickness more slowly than the sputtered, thicker layer.
An etchback step, for example chemical-mechanical polishing, can then be used to remove the thinner layer, while leaving most of the thicker layer intact within the filled feature.
The enhanced resputtering yield of a very thin film allows zero film growth on the underlayer film. However, the lower atomic weight underlayer in the via, made of a material such as TiN, Mo or transition metal silicide, allows the film thickness to increase.